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Overview of Thread Scheduling
Thread Scheduling 4-9
Table 4-2. Thread Preemption
Figure 4-2 shows the execution graph for a scenario in which SWIs and HWIs
are enabled (the default), and a hardware interrupt routine posts a software
interrupt whose priority is higher than that of the software interrupt running
when the interrupt occurs. Also, a second hardware interrupt occurs while the
first ISR is running. The second ISR is held off because the first ISR masks
off (that is, disables) the second interrupt during the first ISR.
Thread Running
Thread Posted HWI SWI TSK IDL
Enabled HWI Preempts Preempts Preempts Preempts
Disabled HWI Waits for
reenable
Waits for
reenable
Waits for
reenable
Waits for
reenable
Enabled, higher-priority SWI —— Preempts Preempts Preempts
Disabled SWI Waits Waits for
reenable
Waits for
reenable
Waits for
reenable
Lower priority SWI Waits Waits —— ——
Enabled, higher-priority TSK —— —— Preempts Preempts
Disabled TSK Waits Waits Waits for
reenable
Waits for
reenable
Lower priority TSK Waits Waits Waits ——
- TMS320 DSP/BIOS 1
- User’s Guide 1
- Read This First 3
- Read This First v 5
- Related Documentation 7
- Trademarks 8
- Contents 10
- Contents xi 11
- Contents 11
- Figures 12
- Contents xiii 13
- Contents xv 15
- Examples 16
- Contents xvii 17
- Examples 18
- About DSP/BIOS 19
- About DSP/BIOS 1-3 21
- 1.2 DSP/BIOS Components 22
- Table 1-1. DSP/BIOS Modules 23
- DSP/BIOS Components 25
- About DSP/BIOS 1-7 25
- Figure 1-3. The DSP/BIOS Menu 26
- Plug-in Toolbars→DSP/BIOS 27
- 1.3 Naming Conventions 28
- 1.3.2 Object Names 29
- 1.3.3 Operation Names 29
- 1.3.4 Data Type Names 30
- 1.3.5 Memory Segment Names 31
- 1.4 For More Information 34
- Program Generation 35
- 2.1 Development Cycle 36
- Using the Configuration Tool 38
- Program Generation 2-5 39
- 2.2.5 Hierarchy Tree View 40
- 2.2.6 Ordered Collection View 40
- Program Generation 2-7 41
- Program Generation 2-13 47
- Program Generation 2-15 49
- 2.4.2 Makefiles 50
- Program Generation 2-19 53
- 2.6 DSP/BIOS Startup Sequence 54
- DSP/BIOS Startup Sequence 55
- Program Generation 2-21 55
- 2.7 Using C++ with DSP/BIOS 58
- Program Generation 2-27 61
- Instrumentation 63
- 3.1 Real-Time Analysis 64
- Real-Time Analysis 65
- Instrumentation 3-3 65
- Instrumentation Performance 66
- Instrumentation 3-5 67
- 3.3 Instrumentation APIs 69
- Instrumentation APIs 70
- →Message Log 70
- HostTarget 71
- →RTA Control Panel. Right 72
- Instrumentation 3-11 73
- →Statistics View 73
- `LOG or STS operation` 78
- Table 3-2. TRC Constants: 79
- TRC_disable(TRC_GBLTARG); 80
- 3.4.1 The Execution Graph 81
- 3.4.2 The CPU Load 82
- Example 3-3. The Idle Loop 84
- 3.4.4 Monitoring Variables 87
- 3.4.5 Interrupt Latency 90
- Kernel/Object View Debugger 91
- 3.5.1 Kernel 92
- 3.5.2 Tasks 93
- 3.5.3 Mailboxes 94
- Instrumentation 3-33 95
- 3.5.4 Semaphores 96
- 3.5.5 Memory 97
- 3.5.6 Software Interrupts 98
- Instrumentation 3-37 99
- 3.7 Real-Time Data Exchange 100
- 3.7.1 RTDX Applications 101
- 3.7.2 RTDX Usage 101
- 3.7.3 RTDX Flow of Data 101
- Real-Time Data Exchange 102
- Instrumentation 3-41 103
- 3.7.4 RTDX Modes 104
- 3.7.6 Target Buffer Size 104
- Instrumentation 3-43 105
- Thread Scheduling 106
- 4.1.1 Types of Threads 107
- Overview of Thread Scheduling 108
- Thread Scheduling 4-3 108
- 4.1.4 Thread Priorities 112
- Figure 4-1. Thread Priorities 112
- 4.1.5 Yielding and Preemption 113
- Table 4-2. Thread Preemption 114
- 4.2 Hardware Interrupts 116
- Hardware Interrupts 117
- Thread Scheduling 4-13 118
- SETC INTM, DEGM 118
- CLRC INTM, DBGM 118
- Thread Scheduling 4-15 120
- Thread Scheduling 4-17 122
- Thread Scheduling 4-19 124
- Thread Scheduling 4-21 126
- `isr code` 127
- Thread Scheduling 4-23 128
- .end 129
- 4.2.5 Registers 130
- 4.3 Software Interrupts 131
- 4.3.1 Creating SWI Objects 132
- Software Interrupts 133
- →Ordered collection view.) 133
- Thread Scheduling 4-29 134
- Thread Scheduling 4-31 136
- Thread Scheduling 4-37 142
- C54x Platform C55x Platform 142
- C6000 Platform 142
- C28x Platform 142
- SWI_enable(key); 143
- Thread Scheduling 4-39 144
- 4.4 Tasks 145
- Thread Scheduling 4-43 148
- Thread Scheduling 4-45 150
- 4.4.4 Task Hooks 152
- Note: 154
- Thread Scheduling 4-51 156
- 4.5 The Idle Loop 158
- The Idle Loop 159
- 4.6 Semaphores 160
- 4.6.1 SEM Example 161
- Semaphores 162
- Thread Scheduling 4-57 162
- Thread Scheduling 4-59 164
- 4.7 Mailboxes 166
- 4.7.1 MBX Example 167
- Mailboxes 168
- Thread Scheduling 4-63 168
- Thread Scheduling 4-65 170
- Thread Scheduling 4-67 172
- Thread Scheduling 4-69 174
- 4.8.2 System Clock 176
- 4.8.3 Example—System Clock 177
- Thread Scheduling 4-73 178
- Thread Scheduling 4-77 182
- →Execution Graph 183
- Thread Scheduling 4-79 184
- Thread Scheduling 4-81 186
- Chapter 5 187
- 5.1 Memory Management 188
- Memory Management 189
- 5.1.5 Freeing Memory 192
- 5.1.8 MEM Example 193
- Example 5-2 196
- 5.2 System Services 197
- 5.2.2 Handling Errors 199
- 5.3 Queues 200
- 5.3.2 Other QUE Functions 201
- 5.3.3 QUE Example 202
- Chapter 6 205
- 6.1 I/O Overview 206
- I/O Overview 207
- 6.3.1 Writing Data to a Pipe 211
- Example 6-3 Using PIP_alloc 215
- Example 6-4 Using PIP_get 215
- Figure 6-4. Binding Channels 217
- 6.5 I/O Performance Issues 219
- Chapter 7 220
- Creating and Deleting Streams 225
- →model) set to 225
- Int SIO_delete(stream) 225
- SIO_Handle stream; 225
- 7.3.1 Buffer Exchange 227
- 7.4 Stackable Devices 235
- Stackable Devices 236
- SIO_get ( ) 236
- SIO_put ( ) 236
- (siotest4.c, siotest4.cdb) 241
- 7.5 Controlling Streams 242
- 7.6.1 Programming Example 243
- 7.9 Device Driver Template 247
- 7.10 Streaming DEV Structures 249
- Streaming DEV Structures 251
- 7.12 Opening Devices 253
- 7.13 Real-Time I/O 257
- Application 258
- SIO_module 258
- Dxx_module 258
- Application SIO_module 258
- 7.14 Closing Devices 260
- 7.15 Device Control 262
- 7.16 Device Ready 262
- Device Ready 263
- 7.17 Types of Devices 265
- Underlying 266
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