Coma FW-C2800 User's Guide download pdf (Page 118)

Hardware Interrupts

Thread Scheduling 4-13

In real-time mode, background codes are suspended at break events while

continuing to execute the time-critical interrupt service routines (also referred

to as foreground code.)

4.2.3.1 Interrupt Behavior for C28x During Real-Time Mode

Real-time mode for C28x is defined by three different states:

❏ Debug Halt state

❏ Single Instruction state

❏ Run state

Debug Halt State: This state is entered through a break event, such as the

decoding of a software breakpoint instruction or the occurrence of an analysis

breakpoint/watchpoint or a request from the host processor.

When halted, time-critical interrupts can still be serviced. An interrupt is

defined as time critical interrupt/real-time interrupt if the interrupt has been

enabled in the IER and DBGIER register. Note that the INTM bit is ignored in

this case.

However, the DBGM bit can be used to prevent the CPU from entering the

halt state (or perform debug access) in undesirable regions of code. If INTM

and DBGM are used together, then it is possible to protect regions of code

from being interrupted by any type of interrupt. It also ensures that debugger

updates of registers/memory cannot occur in that region of code.

SETC INTM, DEGM

/ Uninterruptable, unhaltable region of code

CLRC INTM, DBGM

If the breakpoint is present in real-time, it halts the CPU and causes it to enter

into DEBUG HALT mode. This is identical to the behavior of breakpoints

when in stopmode. Note that software breakpoints replace the original

instruction -- so it is not possible to safely ignore or delay the software

breakpoint’s execution; otherwise, you will not be executing the intended set

of instructions. However, other forms of causes of halting the CPU can be

delayed. It’s important to note that placing software breakpoints is a

"deliberate act" -- you know exactly where you are going to halt, whereas with

other forms of halting (such as via the CCS Halt command or a watchpoint or

other triggering event), the user will often not know where in the program

execution the halt will occur.

The user should never place breakpoints in locations where interrupts or halts

are forbidden. However, it is possible that a halt from a CCS Halt or

watchpoint could be initiated when the CPU is in the uninterruptible,

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Coma FW-C2800 User's Guide Page 118